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TSMC CLN7FF Pre-search and Pipeline Ternary Content Addressable Memory Compiler

Overview

IGMTLSX04A is a synchronous LVT / ULVT periphery high-density pre-search and pipeline ternary content addressable memory (TCAM) with column redundancy feature. It is developed with TSMC 7nm 0.75V/1.8V CMOS LOGIC FinFET Process. Different combinations of words and bits can be used to generate the most desirable configurations. The pre-search scheme is built to reduce average power of Compare operation. Pipeline scheme reduces the cycle time and the access time of Compare and Read operations.
Given the desired size and timing constraints, the IGMTLSX04A compiler is capable of providing suitable synchronous TCAM instances models within minutes. It is capable of automatically generating the data sheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length can be neglected as long as the setup/hold times and minimum high/low pulse widths are satisfied. This allows a more flexible clock falling edge during each operation.

Key Features

  • Ternary Content Addressable Memory (TCAM) operates within a voltage range from 0.675V to 0.825V and a junction temperature range from -40°C to 125°C. The available supported macro size is configured from 64bits to 80K bits.
  • ? Pins and metal layers
  • – 1P5M (1X_h_1Xa_v_1Ya_h_1Y_v): 5 metal layers used and top metal is MY
  • – Power mesh supported with M5 pins
  • ? General feature
  • – TSMC 16T 0.126um2 NOR TCAM bit cell
  • – Full-customized design to optimize for performance, power and area
  • – Two arrays, Data and Mask arrays, used to encode 0, 1 or X
  • – Memory control pins for read/write and compare
  • – Global mask input for bit-write and masked-key search capability
  • – Dynamic compare power saving by appropriately configuring bank enable pins and pre-search
  • – Reduced data access time by pipeline (three-cycle Compare operation and two-cycle Read operation)
  • – Valid bit per entry
  • – MATCHLINE outputs
  • – Column redundancy
  • – Dual rail design to support Dynamic Voltage Frequency Scaling (DVFS) application
  • – Support BIST/ECC code
  • – Frequently used EDA model support
  • ? BIST compiler feature
  • – BIST RTL compiler enabling TCAM complete read, write, search function tests with various data background
  • – At-speed test for column repair TCAM compiler
  • – JTAG interface to program basic and advanced types of algorithm
  • – Hierarchical verification flow: TCAM local, block level and SOC level verification
  • – Support the JTAG stream for various BIST algorithm tests and programmable tests
  • – With eFuse inserted, generate the JTAG stream for BIST tests, eFuse programming and BISR test
  • ? ECC system feature
  • – Pure soft macro RTL compiler to support SEC/DED for Read/Write operation and SCRUB mode
  • – Support auto scrub mode with programmable timing interval
  • – External scrub can be requested by system with interrupt control
  • – External standard SRAM can be used for ECC bits
  • – Support RTL wrapper for system integration and test bench for verification

Technical Specifications

Foundry, Node
TSMC 7nm CLN7FF
Maturity
Pre-silicon
TSMC
Pre-Silicon: 7nm
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