Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 55nm SP process
Overview
UMC 55nm SP/HVT Logic process 7-Track ECO_M1 Cell Library.
Technical Specifications
Foundry, Node
UMC 55nm SP
UMC
Pre-Silicon:
55nm
Related IPs
- Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm SP process
- Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm SP process
- Standard Cell (ECO) Library IP, HVT, 7 tracks, UMC 28nm HPC process
- Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm SP process
- Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm SP process
- Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 28nm HLP process