SM4-XTS Crypto Accelerator

Overview

Key Features

• Widebus interface
• Key size: 128 bits
• Key scheduling in hardware
• Hardware reverse (decrypt) key generation
• Supported modes: ECB and XTS
• Fully synchronous design
• Multiple high-speed versions (4-core, 16-core and 32-core versions)
• Multi-core engine with shared key scheduler for high throughput performance with low area overhead
• Optional: CTS (available on customer request)

Benefits

• EIP-312x-4: 4-core ECB/XTS
  • Throughput: 16 bits/clk achieving 14.4 Gbits/sec at maximum frequency.
  • Maximum frequency 900 MHz in TSMC 28nm LVT.
• EIP-312x-16: 16-core ECB/XTS
  • Throughput: 64 bits/clk achieving 54.4 Gbits/sec at maximum frequency.
  • Maximum frequency 850 MHz in TSMC 28nm LVT.
• EIP-312x-32: 32-core ECB/XTS
  • Throughput: 128 bits/clk achieving 105.6 Gbits/sec at maximum frequency.
  • Maximum frequency 825 MHz in TSMC 28nm LVT.

Deliverables

• Documentation:
  • Hardware Reference and Programmer Manual.
  • Integration Manual.
• Synthesizable Verilog RTL source code.
• Self-checking RTL test bench, including test vectors and expected result vectors.
• Synthesis scripts.

Technical Specifications