RapidIO II 1x/2x/4x at 5G/6.25G supporting 2.2 spec
Overview
The RapidIO® standard was adopted by a significant portion of the wireless industry as a high-speed interconnect and is typically used between digital signal processors and between the control plane processors and memory. RapidIO is also gaining acceptance as a backplane interconnect due to its adoption of widely used standards for the electrical characteristics of the physical media attachment (PMA) such as XAUI or CEI for up to 6.25 Gbaud data rate.
Benefits
- SOPC Builder Ready: No
- Qsys Compliant: Yes
Technical Specifications
Related IPs
- PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- Serial ATA (SATA) I/II PHY IP CORE
- RapidIO
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- Memory Controller for embeded systems supporting SDRAM and NandFlash, with bootstrap loader
- SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process