Public Key Accelerator Farm Engine

Overview

The EIP-154 PKI Farm engine, offers autonoumus processing of Public Key Operations. Due to its scalable architecture, it provides high-performance acceleration of Public Key operations and for power-conscious applications, it can be controlled to reduce its power consumption as utilization is lowered. The Integrated PKA Farm Engine is a FIPS 140-2 compliant Public Key Accelerator operating as a co-processor to offload the Host processor.

Key Features

High-performance accelerator for Public Key operations, up to 4160-bit modulus size for modular exponentiations and 768-bit modulus for ECC operations
Performs high-level key negotiate & sign/verify operations
Synthesizable over 550 MHz in 40nm technologies and over 650 MHz in 28nm technologies
Up to sixteen independent command/result queues
High-Assurance mode with secure boot and protected RAM
Firmware protection bits and fault detection circuitry
ECC/SECDED support option for selected memories
Optional Black Private Key decrypt using AES
Optional high-performance True Random Number Generator for local (and secure) key and signature seed value generation
Two different performance options are available: one with 10 PKA Farm Engines (highest performance) and one with 2 PKA Farm Engines.
The highest performance option uses approximately 1M gates, the 2 Farm Engine configurations uses approximately 350k gates (technology dependent).
8K-bit large vector support options

Benefits

Complete HW/SW system.
High-performance accelerator for public key operations
Silicon-proven IP Design
Dynamic clock management for power efficiency
Supports wide range of applications
Fast and easy to integrate into SoCs.
Flexible layered design.
Software support available:
Complete Firmware Suite Included to provide High-Level Operations
Complete range of configurations.
World-class technical support.

Deliverables

"Documentation

Hardware Reference and Programmer Manual
Integration Manual
Verification Specification

Synthesizable Verilog RTL source code
Self-checking RTL test bench, including test vectors and expected result vectors
Simulation scripts
Synthesis scripts
Many different configurations available:

8K vector support (optional)
2-10 Farm Engines
PLB or asynchronous AHB or APB interface instead of the synchronous AHB or AXI interface.
Gate counts range from : 33-1240K gates, depending on number of modules
Up to 840 MHz
Performance when running at 500 MHz (with 10 Farm Engines operating in parallel):

DH 180/1K-bit exp/mod negotiate: 41,250 ops/sec
RSA 1K-bit sign (no CRT): 8,600 ops/sec; sign (with CRT): 22,630 ops/sec; verify (17 bits exp): 103,000 ops/sec
DSA 160/512-bit exp/mod sign: 46,250 ops/sec; verify: 31,880 ops/sec
ECDSA 192-bit sign: 12,500 ops/sec; verify: 7,630 ops/sec
ECDSA 256-bit sign: 8,520 ops/sec; verify: 4,840 ops/sec
ECDSA 384-bit sign: 4,130 ops/sec; verify: 2,310 ops/sec
ECDSA 521-bit sign: 2,130 ops/sec; verify: 1,190 ops/sec

For more information about this product or the all the different configurations, please contact Rambus: https://www.rambus.com/contact

Technical Specifications

Foundry, Node

Any

Maturity

Silicon Proven

Availability

Now

TSMC

Silicon Proven: 7nm , 16nm , 28nm , 40nm G

Request Info