Precision Power-on Reset Generator
Overview
The Silicon Creations 3-Supply Power-On Reset circuit provides a fi xed width reset pulse for chip initialization after power up. The design senses the voltage level of three supply domains (0.9V, 1.8V, and optionally 3.3V) and initiates the reset pulse when all three supplies are above 80% of the nominal value. The POR includes a built-in bandgap voltage reference circuit and is designed to be insensitive to supply ramp times. Brown-out protection is also included.
Key Features
- Monitors either 2 power domains ( 0.9V & 1.8V ) or 3 power domains ( 0.9V & 1.8V & 3.3V) per selection via digital control input.
- Insensitive to supply ramp up time - minimum suppply ramp time should be dictated by Latchup requirements of IO cells and not POR cell.
- Insensitive to power up/down sequence (order of supply rise/fall does not change circuit behavior)
- Built in Hysteresis to guarantee single pulse operation.
- Multiple output resetB signals in 0.9V and 1.8V domains.
- Brown out detection if any of the supplies drops below 70% of nominal voltage level.
- External reset override ( POR bypass mode ) should
- be supported.
- Supports reset pulse width extension from core side.
- Passes Latch Up checks
Deliverables
- GDSII
- CDL Netlist (MG Calibre Compatible)
- Functional Verilog Model
- Liberty timing models (.lib)
- LEF
- Application Note
Technical Specifications
Foundry, Node
TSMC 28 HPC
Maturity
GDS2
Availability
Now
TSMC
Pre-Silicon:
28nm
HPC
,
28nm
HPM