PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface

Overview

Key Features

• PCI Express layer
  • Designed to the USB4 Specification v1.0
  • Follows PCIe 1.0 protocol, but can operate at any compatible speed
  • Supports the PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
  • Supports Endpoint, Root-Port, Dual-mode configurations
  • Supports up to 64 Physical Functions (PF), 512 Virtual Functions (VF)
  • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, crosslink, and other optional features
  • Additional optional features include LTR, L1 PM substates, etc.
• AMBA AXI layer
  • Compliant with the AMBA® AXI™ Protocol Specification (AXI3, AXI4 and AXI4-Lite) and AMBA® 4 AXI4-Stream Protocol Specification
  • Supports multiple, user-selectable AXI interfaces including AXI Master, AXI Slave, AXI Stream
  • Each AXI interface data width independently configurable in 512-, 256-, 128-, and 64-bit
  • Each AXI interface can operate in a separate clock domain
  • Supported Burst types include INCR, FIXED, WRAP
  • Narrow transfers supported
• Integrity and Data Encryption (IDE)
  • Implements the PCI Express IDE ECN
  • Configurable IDE engine
  • Supports x1 to x16 lanes
  • 256-bit or 512-bit data bus for PCIe IDE
  • Supports containment and skid modes
  • Supports early MAC termination
  • Supports multi-stream
  • Utilizes high-performance AES-GCM for encryption, decryption, authentication
  • PCIe IDE TLP aggregation for 1, 2, 4, 8 TLPs
  • PCIe IDE automatic IDE prefix insertion and detection
  • PCIe IDE automatic IDE sync/fail message generation
  • PCRC calculation & validation
  • Efficient key control/refresh
  • Bypass mode
• Data engines
  • Optional built-in Legacy DMA engine
    • Up to 8 DMA channels, Scatter-Gather, descriptor prefetch
    • Completion reordering, interrupt and descriptor reporting
  • Optional Address Translation tables for direct PCIe to AXI and AXI to PCIe communication

Benefits

• Availability of multiple AXI Master interfaces.
• Wizard enables customization of the IP by setting a vast array of parameters: AXI interfaces, PIPE interface width, low power support, SR-IOV, ECC, AER, etc.
• Advanced features enable fine tuning of power, area, throughput and latency.
• Quickboot mode allows for up to 4x faster link training.
• PCIe to AXI and AXI to PCIe Ordering Rules guarantees AXI deadlock prevention.
• AXI bridge & AXI interconnect allow full performance on AXI interfaces.
• Internal data path size automatically scales up or down (64-, 128-, 256-, 512-bits) based on link max. speed and width for reduced gate count and optimal throughput.
• Each AMBA AXI user interface can be configured independently from 64-bit to 512-bit and with independent clock speeds to provide a variety of connectivity options.
• Stringent verification methodology.
• PCI-SIG compliant multiple times.
• Supports Advanced Reliability,Availability, Serviceability (RAS) features.

Block Diagram

Applications

• USB4 hubs for PC and automotive;
• USB4 hosts in PCs, laptops, gaming, TV and other chipsets;
• USB device adapters including USB4 to NVMe, USB4 to Audio/Video, USB4 eGPU and USB4 to Ethernet.

Deliverables

• IP files
  • Verilog RTL source code
  • Libraries for functional simulation
  • Configuration assistant GUI
• Documentation
• PCI Express® Bus Functional Model
  • Encrypted Simulation libraries
• Reference Designs
  • Synthesizable Verilog RTL source code
  • Simulation environment and test scripts
  • Synthesis project & DC constraint files (ASIC)
  • Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)

Technical Specifications