On-chip AHB SRAM Memory Controller
Overview
CoreAhbSram provides an AHB bus interface to the embedded SRAM memory blocks within Microsemi's Flash devices. In these devices, software running on an AHB-based microprocessor will be able to read and write the embedded SRAM. CoreAhbSram implements a standard Slave AHB Bus 32-bit hardware interface. The core supports the ability to logically merge multiple SRAM blocks into one large area of SRAM.
Key Features
- Optimized for use with Microsemi Flash FPGAs
- Implements Standard Slave AHB Bus Hardware Interface
- 32-Bit Interface, Allowing Byte, Halfword, or Word Accesses to SRAM
- Interfaces to Synchronous or Asynchronous SRAM
- Ability to Logically Merge Multiple SRAM Blocks into One Large Area of SRAM
- Supplied in SysBASIC Core Bundle
Technical Specifications
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