Lossless & Near-Lossless JPEG-LS Encoder

Overview

The JPEG-LS-E core implements a highly-efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard.

Based on LOCO-I (LOw COmplexity LOssless COmpression for Images), the JPEG-LS algorithm leads in numerically lossless compression efficiency, attaining compression ratios similar or superior to those obtained with more advanced algorithms such as JPEG2000. JPEG-LS also enables hardware implementations with a much smaller silicon footprint and lower memory requirements, thanks to its lower computational complexity and line-based processing. Further, the Near-Lossless mode of the JPEG-LS standard makes higher compression ratios and visually lossless compressed images feasible, allowing the user to set the maximum acceptable difference between a reconstructed and an original image sample.

The JPEG-LS-E core delivers the full compression efficiency of the standard in a compact and easy-to-use hardware block. The core interfaces to the system via standardized AMBA® interfaces: it accepts images and outputs compressed data via AXI4-Stream interfaces, and provides access to its control and status registers via a 32-bit APB interface. After its registers are programmed, the core can encode an arbitrary number of images without requiring any further assistance or action from the system. Users can optionally insert timestamps or other metadata in the compressed stream using a dedicated AXI Streaming interface.

The core is designed with industry best practices, and its reliability has been proven through both rigorous verification and silicon validation. The deliverables include a complete verification environment and a bit-accurate software model.

This core can be mapped to any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.

Key Features

  • JPEG-LS Encoder
    • Highly Efficient Numerically Lossless Compression
      • Better compression ratio than most lossless compression algorithms (JPEG2000, PNG, etc.)
    • Near-Lossless Compression
      • Enables greater compression with visually lossless quality by constraining the maximum difference between reconstructed and original image samples
    • Maximum image resolution of 64Kx64K, or higher with via support for oversize image dimension parameters
    • Up to 16 bits per color sample; up to four color components
  • Easy to Use and Integrate
    • Run-time programmable input and encoding parameters
      • Image resolution, number of color components, color depth
      • Maximum reconstruction error, Point-Transform, Local Gradient, Reset Frequency
    • Automatic program-once encode-many operation
    • AXI4-Stream interfaces for image and compressed data, and 32-bit wide APB for register access
    • Dedicated, easy-to-use timestamps interface
  • Versions and Throughput
    • Area-optimized JPEG-LS-E-S: one sample per cycle
      • 40,000 eq. gates and up to 500 Msamples/sec on a typical 28nm technology
    • Throughput optimized JPEG-LS-E-F: synthesis-configurable number of samples per cycle

Block Diagram

Lossless & Near-Lossless JPEG-LS Encoder Block Diagram

Applications

  • The JPEG-LS-E is suitable for systems requiring numerically or visually lossless compression of images or video of potentially high color or greyscale accuracy. Application areas include medical Imaging (DICOM), aerospace imaging or surveillance, and advanced driver assistance systems.

Deliverables

  • The core is available in source code RTL (Verilog) or as an FPGA netlist, and its deliverables include everything required for successful implementation:
    • Sophisticated self-checking Testbench
    • Software (C++) Bit-Accurate Model
    • Sample simulation and synthesis scripts
    • Comprehensive user documentation

Technical Specifications

Maturity
Production Proven
Availability
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Semiconductor IP