The agileLDO is a linear low-dropout voltage regulator (LDO) providing precision and programmable voltage regulation across a wide range of input and output voltages. The regulator architecture provides a high dynamic performance making it suitable for demanding digital applications. Whilst the low noise and high PSSR lends itself to powering noise-sensitive analog circuits.
Linear LDO Low-Dropout Voltage Regulator UMC
Overview
Key Features
- Input Voltage Range: PDK VddIO
- Programmable Output Voltage Range
- Current Load: <1mA to 100mA
- PSRR
- @DC Typ: 40dB
- @1MHz Typ: 20dB
- Load Regulation: Typ 0.3 %/V
- Line Regulation: Typ 50mV/A
- Quiescent current (Iq): Typ 100uA
- Customizable design for simple SoC integration
- Integrated Test Mode
- Silicon Area – Please contact Agile Analog
Benefits
- High Performance
- - Low Noise and High PSSR for noise-sensitive analog circuits
- Sense Input
- - Low Noise and High PSSR for noise-sensitive analog circuits
Block Diagram
Applications
- IoT, Security, Automotive, AI, SoCs, ASICs
Deliverables
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Technical Specifications
Foundry, Node
UMC
Maturity
Available on request
Availability
Now
UMC
Pre-Silicon:
14nm
,
22nm
,
28nm
,
28nm
HLP
,
28nm
HPC
,
28nm
HPM
,
28nm
LP
,
40nm
,
40nm
LP
,
55nm
,
65nm
LL
,
65nm
LP
,
65nm
SP
,
80nm
,
90nm
G
,
90nm
LL
,
90nm
SP
,
110nm
,
130nm
,
150nm
,
162nm