The agileLDO is a linear low-dropout voltage regulator (LDO) providing precision and programmable voltage regulation across a wide range of input and output voltages. The regulator architecture provides a high dynamic performance making it suitable for demanding digital applications. Whilst the low noise and high PSSR lends itself to powering noise-sensitive analog circuits.
Linear LDO Low-Dropout Voltage Regulator TSMC
Overview
Key Features
- Input Voltage Range: PDK VddIO
- Programmable Output Voltage Range
- Current Load: <1mA to 100mA
- PSRR
- @DC Typ: 40dB
- @1MHz Typ: 20dB
- Load Regulation: Typ 0.3 %/V
- Line Regulation: Typ 50mV/A
- Quiescent current (Iq): Typ 100uA
- Customizable design for simple SoC integration
- Integrated Test Mode
- Silicon Area – Please contact Agile Analog
Benefits
- High Performance
- - Low Noise and High PSSR for noise-sensitive analog circuits
- Sense Input
- - Low Noise and High PSSR for noise-sensitive analog circuits
Block Diagram
Applications
- IoT, Security, Automotive, AI, SoCs, ASICs
Deliverables
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Technical Specifications
Foundry, Node
TSMC
Maturity
Available on request
Availability
Now
TSMC
Pre-Silicon:
3nm
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4nm
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5nm
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6nm
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7nm
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10nm
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12nm
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16nm
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20nm
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22nm
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28nm
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28nm
HP
,
28nm
HPC
,
28nm
HPCP
,
28nm
HPL
,
28nm
HPM
,
28nm
LP
,
40nm
G
,
40nm
LP
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45nm
GS
,
45nm
LP
,
55nm
FL
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55nm
G
,
55nm
GP
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55nm
LP
,
55nm
NF
,
55nm
ULP
,
55nm
ULPEF
,
55nm
UP
,
65nm
G
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65nm
GP
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65nm
LP
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80nm
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80nm
GT
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80nm
HS
,
85nm
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90nm
FS
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90nm
FT
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90nm
G
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90nm
GOD
,
90nm
GT
,
90nm
LP
,
90nm
zzz
,
110nm
G
,
110nm
HV
,
110nm
LVP
,
130nm
,
130nm
BCD
,
130nm
BCD+
,
130nm
G
,
130nm
LP
,
130nm
LV
,
130nm
LVOD
,
150nm
G
,
150nm
LV
,
160nm
G
,
160nm
LP
,
180nm
,
180nm
E
,
180nm
ELL
,
180nm
FG
,
180nm
G
,
180nm
LP
,
180nm
LV
,
180nm
ULL