FEC RS (198,194) Encoder IP
Overview
FEC RS (198,194) Encoder core is compliant with standard VESA DisplayPort version 2.0. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. FEC RS (198,194) Encoder IIP is proven in FPGA environment. The host interface of the FEC RS (198,194) Encoder can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
Key Features
- VESA Display Port version 2.0 compliant.
- Supports full FEC encoder functionality.
- Supports Reed Solomon (198,194) FEC, 8-bit symbols.
- Supports two-way interleaving for lane 1, lane 2 and lane 4 modes.
- Supports enable of FEC encoders based on lane mode.
Benefits
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables
- The FEC RS (198,194) Encoder interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User s Guide and Release notes.