CoreUPROMIF_APB APB I/F for uPROM
Overview
Description: CoreUPROMIF_APB is an APB wrapper core that provides read-only access to the uPROM memory block contained within RTG4™ devices over the APB interface, facilitating convenient access to uPROM memory for APB masters. CoreUPROMIF_APB must be instantiated alongside the RTG4UPROM SgCore to access the RTG4™ uPROM memory block and uPROM client configurator. CoreUPROMIF_APB implements a clock prescaler to decouple the maximum APB clock frequency from the 30 MHz maximum frequency constraint imposed by the RTG4UPROM SgCore.
Key Features
- 32-bit APB slave interface
- Maps uPROM locations to word aligned address
- Provides prescaler to generate uPROM clock from PCLK
- Provides 36-bit read data port to present uPROM data to simple fabric slaves
- Prevents reads of invalid locations within uPROM address space
Technical Specifications
Related IPs
- APB I/F for Fabric Ram Block
- USB 2.0 Device Controller (IF Certified)
- APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP
- APB Fundamental Peripheral IP, I2C controller, Soft IP
- Real time clock with APB interface
- Timer with APB interface