Analog Bits’ Integrated Bandgap macro comprehensively addresses typical SOC voltage reference needs in a
fully integrated easy-to-use macro. The Integrated Bandgap macro is fully asynchronous and requires no clock
or other synchronizing signal to work correctly. When the macro is disabled (ENA=0) it supplies 0V. The macro
also includes an integrated ESD for the analog VDDA supply.
Band Gap Voltage Generator - TSMC CLN3E
Overview
Technical Specifications
Foundry, Node
TSMC N3E
TSMC
Pre-Silicon:
3nm
Related IPs
- Band Gap IP, Input: 2.0V - 3.3V, VBG=1.23V, UMC 0.25um Logic process
- Band Gap IP, Input: 1.0V - 1.5V, VBG=0.615V, UMC 0.15um SP process
- Band Gap IP, Input: 1.0V - 1.2V, VBG=0.8V, UMC 0.13um LL/FSG process
- Band Gap IP, Input: 1.2V - 3.3V, VBG=0.615V, UMC 0.18um G2 process
- Band Gap IP, Input: 1.0V - 1.8V, VBG=0.615V, UMC 0.18um LL process
- Band Gap IP, Input: 1.2V - 4V, VBG=0.615V, UMC 0.18um LL process