AHB I/F for Fabric Ram Block
Overview
The CoreAHBLSRAM provides access to the embedded large SRAM (LSRAM)and small SRAM (uSRAM) blocks present on SmartFusion2 SOC FPGA family devices through AHB-Lite slave interface. It facilitates convenient access to SRAM by AHB masters. Read and write transactions on the AHB are converted into corresponding transfers on the LSRAM or uSRAM.
Key Features
- Configurable memory size. Memory size can be configured from 2048 bytes to 139264 bytes, in steps of 2K bytes for LSRAMs (RAM1Kx18)
- Configurable memory size. Memory size can be configured from 512 bytes to 9216 bytes in steps of 512 bytes for uSRAMs (RAM64x18)
- Configurable parameter to access either LSRAM or uSRAM memory
- Ability to logically merge multiple SRAM blocks to form large SRAMs or uSRAMs
- AHB interface with data width of 32-bits
- Support to BUSY output signal from the RAM macros to provide access to the SII interface
Technical Specifications
Related IPs
- APB I/F for Fabric Ram Block
- AHB MultiMatrix Fabric
- This is GPIO Block Configurable on AMBA APB/ AHB Interface with wide configuration option
- Fully Compliant AMBA AHB Lite to AHB (Master) Block
- This is fully protocol Compiaint AHB Master to AXI4 Compliant Protocol Translator Block.
- Fully protocol Compliant AXI4 Slave to AHB Slave Compliant Protocol Translator Block.