600MHz General Purpose Clock Multiplier PLL for 180n CMOS

Overview

Key Features

• Wide range N, M, P integer dividers.
• 40MHz – 600MHz output frequency range.
• Compare frequency range 8MHz – 75MHz.
• 15pS RMS cycle to cycle jitter at 600MHz.
• Startup time 25uS.
• Robust lock-detect function.
• Bypass function.
• -40°C to 140°C temperature operation.
• Available divider selection program.
• Small cell area: 0.03mm2 in 0.18µ CMOS.
• 3mW typical power dissipation.
• 1.8V digital and analog supplies.
• 0.18µ CMOS process compatibility.

Block Diagram

Applications

• Crystal frequency to device internal clock multiplication.
• Communication cores.
• Bus Interface cores.

Deliverables

• Verilog model.
• CDL netlist for LVS.
• Design review documentation.
• GDS format layout.
• Timing files.
• Integration notes.
• Production test notes.

Technical Specifications