32-kHz Bandwidth Reconfigurable Delta-Sigma ADC providing up to 13 ENOB

A solution including an input buffer with programmable gain, followed by a Delta Sigma Modulator (DSM) and a Decimation filter is provided. Additionally, the voltage reference buffers, the current generation and DC bias generators are integrated within this solution.
The input impedance is resistive and hence can be easily driven by the preceding stage which may be another analog block or even directly a sensor. Furthermore, the input buffer can be configured to accept either
single-ended or differential voltage inputs making it more convenient to interface with single-ended output blocks/sensors.
The DSM outputs an oversampled single bit stream which is input to an internal decimation filter to filter off the high-frequency noise. The decimation
factor is configurable and hence the output data rate can be increased or decreased by trading off with performance as and when required. Additionally, aprovision is made to output both the 16-bit word from
the decimation filter and the oversampled 1-bit stream from the DSM, as and when demanded.