The 32-bit SSRAM/PROM Controller IP cores is an 32-bit SSRAM/PROM/IO controller that interfaces
external Synchronous pipelined SRAM, PROM, and I/O to the AMBA AHB bus. The controller acts as a slave on the AHB bus and has a configuration register accessible through an APB slave interface.
32-bit SSRAM/PROM Controller
Overview
Key Features
- AMBA AHB interface
- AMBA APB slave interface
- Low area consumption
- Compatible with AMBA-2.0
Deliverables
- VHDL source code
- Synplify project file
- VHDL test bench
- Template design for LEON3 processor
- FPGA evaluation board (optional)
Technical Specifications
Foundry, Node
Any
Maturity
Production
Availability
Immediate