25GbE TCP Offloading Engine(TOE25G-IP) IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE25G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate TOE25G-IPcore on real board before purchasing.
25GbE TCP Offloading Engine
Overview
Key Features
- TCP/IP off-loading engine for 10/25GBASE-R
- Support IPv4 protocol
- Support one port connection (Support Multi-session by implementing multiple cores)
- Supports Full Duplex communication
- Support both Server and Client mode (Passive/Active open and close)
- Support Jumbo frame
- Transmitted packet size aligned to 128-bit, bus size of transmit data
- Total received data size aligned to 128-bit, bus size of received data
- Transmit/Receive buffer size, programmable on HDL for optimized resource
- Simple data interface by 128-bit FIFO interface
- Simple control interface by 32-bit Register interface
- 64-bit AXI4 stream to interface for 10G/25G Ethernet MAC
- User clock frequency must be more than or equal to 195.3125 MHz for 25Gb Ethernet
- Support 10GbE by using DG 10GbEMAC-IP and PCS
- Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
- Reference design is included in IP core product
Block Diagram
