12-bit SAR ADC Samsung

Overview

The agileADC analog-to-digital converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 12-bit resolution at sample rates up to 64 MSPS. It includes a 16-channel input multiplexor that can be configured to be buffered or unbuffered, and support differential or single-ended inputs.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options.

For a further product information, please contact sales@agileanalog.com

Key Features

Resolution: 12 bits
Sampling Rate (Fs) 1: Up to 64 MSPS
Input Signal Bandwidth: Fs/2
SINAD1: Typ 69 dB
ENOB1: Typ 11.3 bits
SFDR1: Typ 90 dBc
INL: +/2 LSB
DNL: +/-1 LSB
Monotonic and no missing codes
Up to 16 input channels
Integrated reference generator
Integrated calibration mode
Silicon area – Please contact Agile Analog

Benefits

Digitally Wrapped
- AMBA-APB Interface to simplify integration, testing and operation.
- Provided with System Verilog models
DFT/DFM
- Incorporated trim and calibration to facilitate process and/or manufacturing offsets to be adjusted
- Built-in test mode
Configurable Inputs
- Up to 16 input channels
- Buffer or unbuffered
- Differential or Single-ended

Block Diagram

Applications

IoT, Security, Automotive, AI, SoCs, ASICs

Deliverables

Datasheet
Testing and Integration Guide
Verilog Models
Floorplan (LEF)
Timing models (LIB)
Netlist (CDL)
Layout (GDS)
Physical Verification Report
Design Report

Technical Specifications

Foundry, Node

Samsung

Maturity

Available on request

Availability

Now