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SD Controller IP

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Search (29)
Compare 29 SD Controller IP from 11 vendors (1 - 10)
  • SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
    • Memory Card / Form Factors:
    • IP Details:
    Block Diagram -- SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
  • SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
    • Compliant with SD Specifications Part 1 UHS-II Addendum v1
    • Supports data rate between 390 Mbps to 1.56 Gbps per lane
    • Supports peak interface speed of 3.12 Gbps in Half-duplex mode; 1.56 Gbps in Full-duplex mode
    • Sub-LVDS differential PHY signaling
    Block Diagram -- SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
  • Block Diagram -- SD 4.1 SDIO 4.1 Host Controller IP
  • SD 3.0 / SDIO 3.0 Combo Device Controller
    • Meets SD Memory Card Physical Layer Specification version 3.0
    • Meets SDIO card specification ver 3.0
    • Host clock rate variable between 0 and 208 MHz
    • All SD bus modes supported including SPI, 1 and 4 bit SD.
    Block Diagram -- SD 3.0 / SDIO 3.0 Combo Device Controller
  • SD/eMMC Host Controller
    • Supports selection between SD and eMMC
    • Supports CRC7 and CRC16 generation and verification on Hardware
    • Supports multiple block transfer
    Block Diagram -- SD/eMMC Host Controller
  • SD 4.0 UHS-II PHY in TSMC 40LP
    • Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II
    • Specification Volume 1: System and Protocol”
    • Per lane data rate between 390Mb/s to 1.56Gb/s
    • Supports peak interface speed of 3.12Gb/s (Half-duplex); 1.56Gb/s in Full-duplex mode
    Block Diagram -- SD 4.0 UHS-II PHY in TSMC 40LP
  • SD/eMMC Lite Host Controller IP
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Lite Host Controller IP
  • SD/eMMC Host Controller IP
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Host Controller IP
  • SD/eMMC Crypto Host Controller
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Crypto Host Controller
  • LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17)
    • Support 1KB+/2KB+/4KB+ codeword size for one time configuration
    • Support code rate (CR) range 0.93~0.83(down to 0.71)
    • Support configurable throughput, ranges from 300MB/s to 16GB/s
    • Support hard-bit decode (HBD) and up to 6bit soft-bit decode (SBD)
    Block Diagram -- LDPC Error Correction Core IP (for SSD, silicon proven, UBER<1E-17)
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