Clock Generator PLL IP for TSMC

Compare 208 Clock Generator PLL IP for TSMC from 9 vendors (1 - 10)

General-purpose & Specialized Ring PLLs + RTL-based Solutions
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
Fractional-N PLL for Performance Computing in TSMC N6/N7
- Frequencies up to 4GHz
- Low jitter (< 10ps RMS)
- Small size (< 0.01 sq mm)
High Speed Low Jitter 16GHz Output LC PLL
- Type II, 3rd order low Jitter PLL
- Auto calibration for process and temperature (USP)
- Programmable frequency using CSR registers
4-GHz Jitter-optimized low-power digital PLL
- - Jitter below 10-ps
- - Super small: 90 x 90 microns!
- - Very low power: 15-mW
- - Broad frequency range: 4-GHz
14GHz Integer-N High-Speed PLL
- Type II hybrid Integer-N LC-PLL
- Quadrature clocks at 14GHz and 7GHz
- Fast locking
100 to 1200MHz phase-locked loop
- TSMC CMOS 55 nm
- Output frequency range from 100 MHz to 1200 MHz
- Fully integrated VCO