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Memory Interface IP for GLOBALFOUNDRIES

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Compare 31 Memory Interface IP for GLOBALFOUNDRIES from 7 vendors (1 - 10)
  • SATA PHY
    • Serial ATA II Revision 2.6 compliant
    • Gen1i, Gen1m, Gen2i, Gen2m compliant
    • Gen1x, Gen2x compatible
    • Initialization and power saving modes
    Block Diagram -- SATA PHY
  • LPDDR5/4/4X PHY - GF 12LP+ for Automotive ASIL B Random, AEC-Q100 Grade 1
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - GF 12LP+ for Automotive ASIL B Random, AEC-Q100 Grade 1
  • LPDDR5/4/4X PHY - GF 12LP+
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - GF 12LP+
  • DDR5/4 PHY - GF 12LP+
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5/4 PHY - GF 12LP+
  • LPDDR5T / LPDDR5X / LPDDR5 Controller
    • Support for all LPDDR5T/5X/5 devices
    • Bank management logic monitors status of each bank
    • Queue-based user interface with reordering scheduler
  • Bi-directional High speed interface lane up to 12.5Gbps
    • High data rate (Up to 12.5Gbps per lane)
    • Programmable receiver frontend
    • Programmable transmitter
    • 5-bit controlled digital delay line in the receiver for high-speed clock
  • SATA 6G PHY in GF (40nm, 28nm)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • LPDDR5/4/4X PHY in GF (12nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR5 SDRAMs up to 6400 Mbps
    • Compatible with JEDEC standard LPDDR4 and LPDDR4X SDRAMs up to 4267 Mbps
    • DFI 5.0 compliant interface to the memory controller
  • LPDDR4X multiPHY Plus in GF (12nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • LPDDR4X multiPHY in GF (14nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
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