MIPI D-PHY IP for GLOBALFOUNDRIES

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Compare 32 MIPI D-PHY IP for GLOBALFOUNDRIES from 8 vendors (1 - 10)

MIPI D-PHY CSI-2 TX (Transmitter) in GlobalFoundries 22FDX
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Alliance Specification for D-PHY Version 2.1
MIPI DPHY Receiver on GF55LPe
- MIPI D-PHY version 1.2 compliant PHY receiver
- Consists of 4 data lane and 1 clock lane
MIPI DPHY & LVDS Transmit Combo on GF55LPe
- MIPI D-PHY version 1.2 compliant PHY transmitter
- OpenLDI version 0.9 compliant LVDS transmitter
MIPI DPHY-RX
- Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps
- Silicon proven in GlobalFoundries 22FDX process
- Compliant to the MIPI D-PHY spec v1.2
- Lane type:1 clock + 4 data(D0 is bi-dir)
- Support for DPHY Ultra Low Power State
MIPI DPHY-TX - GlobalFoundries 22FDX process
- Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps
- Silicon proven in GlobalFoundries 22FDX process
- Compliant to the MIPI D-PHY spec v1.2
- Support HiSPi-SLVS TX compatible mode
MIPI DPHY
- Silicon proven in 22, 28, 55, 110nm from Global Foundries, Samsung and SMIC
- Compliant to the MIPI D-PHY spec v1.1 (SEC28/SMIC55/SMIC110)
- Lane type:1 clock + 4 data, bi-directional
- Built-in self test function
MIPI D-PHY Tx 4 Lanes - GF12LP18, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
MIPI D-PHY Rx 4 Lanes - GF12LP18, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
MIPI DPHY Gen2 Rx-Only 4 Lanes - GF 28SLP 1.8V, East/West Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
MIPI DPHY Gen2 Rx-Only 2 Lanes - GF 28SLP 1.8V, East/West Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes