ETHERNET 10G XAUI PCS IP

Overview

Key Features

• Supports IEEE Standard 802.3.2018 Clause 48 for XAUI PCS
• Supports 8b/10b encoding on each lane to generate code groups in transmit path
• Supports 10b/8b decoding on each lane to convert received code groups to 32 XGMII data bits and 4 XGMII control bits
• Supports synchronization of code groups on each lane to determine code group boundaries
• Supports deskew of received code-groups from all lanes to an alignment pattern
• Supports conversion of XGMII Idle control characters to (from) a randomized sequence of code-groups to enable serial lane synchronization, clock rate compensation and lane-to-lane alignment
• Supports Loopback Functionality
• Support link fault and error indications
• Supports IEEE Standard 802.3az Energy Efficient Ethernet
• Supports Configurable Management Interface (MDIO(Clause 45) / SOC Bus)
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to Microprocessor/Microcontroller devices

Benefits

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The Ethernet interface is available in Source and netlist products.
• The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases.
• Lint, CDC, Synthesis, Simulation Scripts with waiver files.
• IP-XACT RDL generated address map.
• Firmware code and Linux driver package.
• Documentation contains User s Guide and Release notes.

Technical Specifications