eCPRI Controller IP
Overview
eCPRI Controller interface provides full support for the two-wire eCPRI Controller synchronous serial interface, compatible with eCPRI specification v2.1. Through its eCPRI Controller compatibility, it provides a simple interface to a wide range of low-cost devices. eCPRI Controller IIP is proven in FPGA environment.The host interface of the eCPRI Controller can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
Key Features
- Compliant with eCPRI Specification v2.1
- Supports complete eCPRI Tx/Rx Functioanlity
- Supports various Ethernet Speeds - 10G/25G/40G/100G
- Supports rich configuration to handle multi mode wireless systems
- Supports Control and Management data transfer.
- Supports data transfer through Ethernet/UDP/IP Interfaces.
- Supports delay management.
- Supports programmable packet queue to hold frames when eCPRI frame is in progress
- Supports 8B/10B line coding
- Supports following message types
- -> IQ Data
- -> IWF Start Up
- -> IWF Operation
- -> Generic Data Transfer
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
Benefits
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables
- The eCPRI Controller interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog or VHDL or SystemC source code
- Integration testbench and tests
- Scripts for simulation and synthesis with support for common EDA tools
- Documentation contains User s Guide and Release notes.