DDR Controller IP

Overview

Key Features

• Supports DDR protocol standard JESD79F Specification.
• Compliant with DFI-version 2.0 or higher Specification.
• Supports all the DDR commands as per the specs.
• Supports up to 16 AXI ports with data width upto 512 bits.
• Supports controllable outstanding transactions for AXI write and read channels
• Supports in port arbitration and multi port arbitration.
• Supports user programmable page policy.
  • -> Closed page policy
  • -> Open page policy
• Supports Error Checking and correction (ECC).
• Supports retry on ECC error, with retry limit user controllable.
• Supports high clock speeds in ASIC and FPGA.
• Supports low latency for write and read path.
• Supports reordering of transactions for higher performance.
• Supports all device speeds as per specification.
• Supports Programmable CAS latency.
• Supports Programmable burst lengths: 2,4 and 8.
• Supports Write data Mask.
• Supports the following devices.
  • -> X4
  • -> X8
  • -> X16
• Supports the following memory densities.
  • -> 64MB
  • -> 128MB
  • -> 256MB
  • -> 512MB
  • -> 1GB
• Supports the following burst types.
  • -> Sequential
  • -> Interleave
• Supports burst order.
• Supports for All Mode registers programming.
• Supports for Extended Mode registers programming.
• Supports Auto refresh & self refresh modes.
• Supports Auto precharge option for each burst access.
• Supports Power Down features.
• Supports input clock stop and frequency change.
• Supports DLL operation.
• Fully synthesizable
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The DDR interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases.
• Lint, CDC, Synthesis, Simulation Scripts with waiver files.
• IP-XACT RDL generated address map.
• Firmware code and Linux driver package.
• Documentation contains User s Guide and Release notes.

Technical Specifications