Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to an AXI4-Stream TID, and sends the data with TID out on the AXI4-Stream Interface.
The DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE IP Core works with Digital Blocks DMA Controller (i.e. the DB-DMAC-MC-AXI Verilog RTL IP Core) to transfer data from either memory or a peripheral to an AXI4-Stream peripheral or AXI4-Stream Network Interface.
AXI4 Memory Map to AXI4-Stream Bridge
Overview
Key Features
- Converts AXI4/AXI3 Memory Map Data & Control Interface into AXI4-Stream Interface
- Standard release supports 16 AXI4-Stream Channels.
- More or less Channels optional. Contact Digital Blocks with requirements.
- Works with Digital Blocks DMA Controller to support following data transfers:
- Memory-to-Peripheral
- Memory-to-Network
- Peripheral-to-Peripheral
- Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024.
- Interrupt Controller – for Diagnostics
Deliverables
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Technical Specifications
Foundry, Node
TSMC, GlobalFoundaries, UMC, Samsung, SMIC, Intel, Tower Jazz, Powerchip
Maturity
Successful in Customer Implementations
Availability
Immediately
Related IPs
- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
- DMA AXI4-Stream Interface to AXI Memory Map Address Space
- SPI to AXI4 Controller Bridge
- Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
- CMOS to MIPI CSI-2 Interface Bridge IP