The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
Control is managed by Commands that stream in via dedicated Command, AXI4-Stream Interfaces, with resulting output Status on Status Stream, AXI4-Stream Interfaces.
Digital Blocks offers two version releases of the DB-DMAC-MC2-CS-MM2S-S2MM:
• High AXI bandwidth throughput version with internal control plane that keeps the data interfaces transferring data at the full AXI Interface capabilities.
• Nominal bandwidth throughput version requiring less control plane VLSI resources at a lower licensing cost
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
Overview
Key Features
- 2 Dedicated DMA Channels, 1 each for data transfers for the following:
- MM2S: AXI4-Memory Map Read Data to AXI4-Stream Write Data
- S2MM: AXI4-Stream Read Data to AXI4-Memory Map Write Data
- Command and Status via AXI4-Stream Interfaces - 1 set per MM2S & S2MM:
- Control input via Command AXI4-Stream Interfaces
- Status output via Status AXI4-Stream Interfaces
- Commands & Status FIFOs for Queuing - Parameters for depth
- MM2S & S2MM DMA Controllers:
- Read & Write DMA Controller Engines
- Data FIFO - Parameters for width and depth
- Unaligned data transfers with byte realignment & using byte strobes
- Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024.
- Programmable Data Burst Capability: 1, 4, 8, 16 (fixed) and 1 – 256 (AXI4)
- 4 KB boundary crossing detection & resizing of AXI transaction
- Compliance with AMBA Specifications:
- AXI4 Protocol Specification (Memory Map Read/Write Channels)
- AXI4-Stream Protocol Specification
- Fully synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASIC design flows.
Block Diagram
Deliverables
- Verilog RTL Source or technology-specific netlist.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation & Implementation Guide.
- Technical Reference Manual.
Technical Specifications
Maturity
Successful in Customer Implementations
Availability
Immediately
Related IPs
- DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
- Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
- AXI4 to/from AXI4-Stream Scatter-Gather DMA
- DMA AXI4-Stream Interface to AXI Memory Map Address Space
- AXI4 Memory Map to AXI4-Stream Bridge
- AXI4 Memory-Mapped to/from AXI4-Stream DMA