UDP/IP Hardware Protocol Stack - 25G

Overview

The Digital Blocks DB-UDP-IP-25GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 25 GbE network links. The DB-UDP-IP is a Verilog SoC IP Core targeting Intel/Altera and Xilinx FPGAs and ASIC/ASSP devices.

Key Features

  • 25 GbE network links
  • Low latency, high-performance wire-line performance
  • Internet Protocol (IP) Packet Processor:
    • IP & ICMP (Internet Control Message Protocol) Protocol
    • Host IP address filter, IP header checksum check & generator, user-selectable Maximum Transmission Unit (MTU), Unicast & Multicast Packet support
    • Compliance with IETF IPv4/IPv6 RFCs
  • User Datagram Protocol (UDP) Packet Processor:
    • Support for up to 256 UDP Ports
    • UDP header checksum check & generator
    • Compliance with IETF UDP RFCs
  • Address Resolution Protocol (ARP) Packet Processor (client/server) with 4-16 entry ARP cache
  • VLAN Support, DHCP, IGMP, Jumb Frames
  • Interface to Intel/Altera (Avalon-ST) & Xilinx & Synopsys 25G MAC
  • High Speed Data Interface to user Host Application:
    • 256-bit / 512-bit AXI4-Stream
  • Host set-up & control via Control & Status Registers and Interrupt Controller
    • 32-bit AXI4-Lite or APB or AHB
  • Pipeline, High Clock Rate, Low Latency architecture & design
  • Fully-synchronous, synthesizable RTL Verilog SoC IP core

Deliverables

  • Verilog RTL Source or technology-specific netlist.
  • Comprehensive testbench suite with expected results.
  • Synthesis scripts.
  • Installation & Implementation Guide.
  • Technical Reference Manual.

Technical Specifications

Foundry, Node
IBM, LSI, TMSC, UMC, Tower, Tower, GlobalFoundaries
Maturity
Successful in Company FPGA Kit Demo Reference Design, Customer Products
Availability
Immediately
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Semiconductor IP