VeriSilicon SMIC 0.13um Synchronous Two-Port Register File optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic 1P8M Salicide 1.2/2.5(3.3)V process.
While satisfying speed and power requirements, it was optimized for area efficiency.
VeriSilicon SMIC 0.13um Synchronous Two-Port Register File uses four metal layers within the blocks and supports metal 6,7,8 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
SMIC 0.13um High-Speed Synchronous Two-Port Register File
Overview
Key Features
- Two Ports (one read and one write)
- High Density
- High Speed
- Size Sensitive Self-time Delay for Fast Access Time
- Automatic Power Down
Deliverables
- Databook in electronic format
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
Technical Specifications
Foundry, Node
SMIC 0.13um
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV
Related IPs
- SMIC 0.13um High-Speed Synchronous Single-Port/Dual-Port SRAM
- Synchronous single-port, dual-port, and two-port register files
- VeriSilicon SMIC 0.13um High-Speed Synchronous Single-Port SRAM compiler, Memory Array Range:256 to 128K Bits
- SMIC 0.13um 90% shrunk Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- SMIC 0.13um 90% shrunk HVT Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
- SMIC 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler