On-chip APB SRAM Memory Controller
Overview
CoreAPBSRAM provides an APB bus interface to the embedded SRAM memory blocks within Microsemi's Flash devices. In these devices, software running on an APB-based microprocessor will be able to read and write the embedded SRAM. CoreAPBSRAM implements a standard Slave APB Bus 32-bit hardware interface. The core supports the ability to logically merge multiple SRAM blocks into one large area of SRAM.
Key Features
- Optimized for use with Microsemi Flash FPGAs
- Implements Standard Slave APB Bus Hardware Interface
- 32-Bit Interface, Allowing Byte, Halfword, or Word Accesses to SRAM
- Interfaces to Synchronous or Asynchronous SRAM
- Ability to Logically Merge Multiple SRAM Blocks into One Large Area of SRAM
- Supplied for free in Libero Catalog
Technical Specifications
Related IPs
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- On-chip Nonvolatile APB Memory Controller
- Avalon Multi-port DDR2 Memory Controller
- I3C Master / Slave Controller w/FIFO (APB Bus)
- DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
- This fifo access external OnChip dual port memory to store data.