High-Performance Single Data Rate SDRAM Controller
Overview
Description: CORESDR provides a high performance interface to single data rate(SDR) synchronous dynamic random access memory(SDRAM) devices. CORESDR accepts read and write commands using the simple local bus interface, and translates these requests to the command sequences required by SDRAM devices. CORESDR also performs all initialization and refresh functions. CORESDR uses bank management techniques to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to four banks can be managed at one time.
Key Features
- Interfaces to External RAM
- Supports up to 1024Mbytes of Memory
- Synchronous Interface
- Supports All Standard SDRAM Chips and DIMMs
- High-Performance Access Logic Allows Cascading of Read and Write Requests
- Bank Management Logic Monitors Status of Each SDRAM Bank (Up to Four Banks Monitored)
- Pipelined Design Enables High Clock Rates with Minimal Routing Constraints
- Netlist, evaluation and RTL versions
Technical Specifications
Related IPs
- High-Performance Single Data Rate SDRAM Controller
- Double Data Rate SDRAM Controller
- Mobile Single Data Rate SDRAM Controller
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