8-10 bit DAC TSMC
Overview
The agileDAC GP is a digital-to-analog converter that uses a traditional capacitive DAC architecture. The agileDAC uses its own internal reference voltage. The architecture can achieve up to 10-bit resolution at sample rates up to 16 Msps.
Key Features
- Resolution: 8b/10b,
- Sampling Rate (Fs): up to 16Msps
- Output Signal Bandwidth: Typ Fs/2
- Guaranteed monotonic
- SFDR1: Typ -60dBc
- INL: Max2 ±4LSB
- DNL: Max2 ±2LSB
- Conversion Time: Typ 2 cycles
- Quiescent current3 (Iq):Typ 250uA
- Customizable design for simple SoC integration
- Integrated Calibration Mode
- Silicon Area – Please contact Agile Analog
Benefits
- DFT/DFM
- - AMBA-APB Interface to simply test and operation
- - Built-in Trim and Calibration to facilitate process and/or manufacturing offsets to be adjusted
Applications
- IoT, Security, Automotive, AI, SoCs, ASICs
Deliverables
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Technical Specifications
Foundry, Node
TSMC
Maturity
Available on request
Availability
Now
TSMC
Pre-Silicon:
3nm
,
4nm
,
5nm
,
6nm
,
7nm
,
10nm
,
12nm
,
16nm
,
20nm
,
22nm
,
28nm
,
28nm
HP
,
28nm
HPC
,
28nm
HPCP
,
28nm
HPL
,
28nm
HPM
,
28nm
LP
,
40nm
G
,
40nm
LP
,
45nm
GS
,
45nm
LP
,
55nm
FL
,
55nm
G
,
55nm
GP
,
55nm
LP
,
55nm
NF
,
55nm
ULP
,
55nm
ULPEF
,
55nm
UP
,
65nm
G
,
65nm
GP
,
65nm
LP
,
80nm
,
80nm
GT
,
80nm
HS
,
85nm
,
90nm
FS
,
90nm
FT
,
90nm
G
,
90nm
GOD
,
90nm
GT
,
90nm
LP
,
90nm
zzz
,
110nm
G
,
110nm
HV
,
110nm
LVP
,
130nm
,
130nm
BCD
,
130nm
BCD+
,
130nm
G
,
130nm
LP
,
130nm
LV
,
130nm
LVOD
,
150nm
G
,
150nm
LV
,
160nm
G
,
160nm
LP
,
180nm
,
180nm
E
,
180nm
ELL
,
180nm
FG
,
180nm
G
,
180nm
LP
,
180nm
LV
,
180nm
ULL