台积电(TSMC)集中R&D人力开发3nm工艺流程
Julien Happich, EETimes
10/4/2016 10:46 AM EDT
PARIS — Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) will actively develop 5-nanometer process technology, while dedicating between 300 and 400 R&D personnel in developing a 3-nanometer process, ultimately aiming at the 1-nanometer manufacturing process, reports Taiwanese magazine CTimes.
In an interview, Dr. Mark Liu, President and Co-Chief Executive Officer of TSMC, said the company will use its three-dimensional stacked architecture technology to break the limitation of Moore's law and move toward the 3nm manufacturing node.
Liu stressed that TSMC has established the complete ecosystems with the intellectual property, automation solutions and equipment providers, and will continue to invest in technology development and research, and to make Taiwan become the strongest fortress in the global semiconductor industry.
Related Semiconductor IP
- 112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
- 112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
Related News
- 新思科技IP 组合在台积公司3纳米工艺上实现首次流片成功,加速先进芯片设计
- 聯發科技採用台積公司3奈米製程生產的晶片已成功完成設計定案 預計於2024年量產
- 新思科技数字和定制设计平台获台积公司最新3纳米制程技术认证
- 新思科技PrimeLib统一库表征和验证解决方案获三星5nm、4nm和3nm工艺认证