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SD PHY IP

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Search (12)
Compare 12 SD PHY IP from 5 vendors (1 - 10)
  • SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
    • Compliant with SD Specifications Part 1 UHS-II Addendum v1
    • Supports data rate between 390 Mbps to 1.56 Gbps per lane
    • Supports peak interface speed of 3.12 Gbps in Half-duplex mode; 1.56 Gbps in Full-duplex mode
    • Sub-LVDS differential PHY signaling
    Block Diagram -- SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
  • 1.8V/3.3V Switchable GPIO With 5V I2C Open - Drain & Analog Cells in Samsung 11nm LPP
    • Multi-voltage 1.8V / 3.3V switchable operation
    • 4 selectable drive strengths (25-235 MHz @ 1.8V, 10pF
    • Full-speed output enable
    Block Diagram -- 1.8V/3.3V Switchable GPIO With 5V I2C Open - Drain & Analog Cells in Samsung 11nm LPP
  • Secure Digital I/O offerings
    • Secure Digital
    • Physical Features
    Block Diagram -- Secure Digital I/O offerings
  • 1.8V/3.3V Switchable GPIO With 5V I2C Open Drain & Analog in 16/12nm
    • Multi-voltage 1.8V / 3.3V switchable operation
    • 4 selectable drive strengths (25-235MHz @1.8V, 10pF)
    • Full-speed output enable
    • Independent power sequencing
    Block Diagram -- 1.8V/3.3V Switchable GPIO With 5V I2C Open Drain & Analog in 16/12nm
  • SD 4.0 UHS-II PHY in TSMC 40LP
    • Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II
    • Specification Volume 1: System and Protocol”
    • Per lane data rate between 390Mb/s to 1.56Gb/s
    • Supports peak interface speed of 3.12Gb/s (Half-duplex); 1.56Gb/s in Full-duplex mode
    Block Diagram -- SD 4.0 UHS-II PHY in TSMC 40LP
  • SD 5.1 / eMMC 5.1 Host Controller IP
    • SD IP Features :
    • Support SD system specification version 5.1
    • Support Application Performance Class 1.
    • Backward compatible to SD2.0 host
    Block Diagram -- SD 5.1 / eMMC 5.1 Host Controller IP
  • TSMC 3nm (N3E) 1.8V SD/eMMC PHY
    • Completely hardened PHY solution along with programmable delay chains & I/Os
    • Fully selectable output impedance
    • Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
    • Automotive G1/G2 supported, ASIL-B certified
  • SD 4.1 UHS-II PHY for TSMC 12nm FF
    • Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II Specification Volume 1: System and Protocol”
  • SD 4.0 Device Controller
    • Compliant with SD Specification 4.0
    • Transfers up to 312 MB/s (UHS156, 52MHz) and supports Half duplex(312 MB/s) and Full duplex (156 MB/s) in SD4.0 mode
    • Low voltage and low power consumption with enhanced power management using new power Control mode by allowing LPS (Low power states like – EIDL and DORMANT)
    • High-performance UHS-II PHY or UHS-I Host connection
  • UHS-II PHY for SD4/SD5 TSMC 12nm FF
    • Compliant with SD Specifications Part 1 UHS-II Addendum v1
    • Supports data rate between 390 Mbps to 1.56 Gbps per lane
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