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LPDDR5 IP

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Compare 89 LPDDR5 IP from 10 vendors (1 - 10)
  • LPDDR5X DDR Memory Controller
    • JEDEC LPDDR5X/LPDDR5 devices compatible
    • Data rates up to 8533Mbps
    • Multiple ARM AMBA AXI4/AHB/APB & Custom interfaces
    Block Diagram -- LPDDR5X DDR Memory Controller
  • DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
    • Compliant with JEDEC standard for LPDDR5/4/3, DDR4/3
    • DRAM rank of up to 4
    • Lock-step-based controlling of multiple DRAM devices up to x64 DQ width
    • Support for dynamic DRAM frequency scaling
    Block Diagram -- DDR4/3, LPDDR5x/5/4x/4 Memory Controller IP
  • LPDDR5/4x/4 combo PHY on 14nm, 12nm
    • JESD209-5A(LPDDR5), JESD209-4C(LPDDR4), JESD209-4-1(LPDDR4X) compliant
    • Operating speed up to 6400Mbps in LPDDR5, 4266Mbps in LPDDR4X
    • Multiple DFICLK : CK :WCK ratios
    Block Diagram -- LPDDR5/4x/4 combo PHY on 14nm, 12nm
  • LPDDR5X/5/4X/4 Memory Controller IP
    • Intensive DRAM Utilization
    • Ultra Low Power Consumption
    • Extremely Low Latency
    • Safety & Security
    Block Diagram -- LPDDR5X/5/4X/4 Memory Controller IP
  • LPDDR5X/5/4X/4 combo PHY at 12nm
    • Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
    • Delivering up to 8533Mbps
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at 12nm
  • LPDDR5X/5/4X/4 PHY for 16nm
    • Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
    • DFI 5.0 Interface Compliant
    • Supports up to 4 ranks
    Block Diagram -- LPDDR5X/5/4X/4 PHY for 16nm
  • LPDDR5/4x/4 PHY IP for Samsung 14LPU
    • Compliant with PHY standards
    • Flexible Configuration
    • Maximum data rates
    Block Diagram -- LPDDR5/4x/4 PHY IP for Samsung 14LPU
  • LPDDR5/4/4X PHY - TSMC N7 for Automotive, ASIL B Random, AEC-Q100 Grade 2
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - TSMC N7 for Automotive, ASIL B Random, AEC-Q100 Grade 2
  • LPDDR5/4/4X PHY - TSMC N7
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - TSMC N7
  • LPDDR5/4/4X PHY - TSMC N6
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - TSMC N6
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