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LPDDR4 Controller IP

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Compare 8 LPDDR4 Controller IP from 6 vendors (1 - 8)
  • LPDDR4/3, DDR4/3 Memory Controller IP
    • Compliant with JEDEC standards for LPDDR4/3, DDR4/3
    • DRAM rank of up to 4
    • Lock-step-based controlling of multiple DRAM devices up to x64 DQ width
    • Support for dynamic DRAM frequency scaling
    Block Diagram -- LPDDR4/3, DDR4/3 Memory Controller IP
  • DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
    • Support DDR3 / DDR3L / DDR4/ 3DS DDR4/ LPDDR4 / MRAM
    • Support x8/x16/x32 DRAM data bus configuration (programmable)
    • Support Multi-Ranks DRAM configuration
    • DDR base on DFI spec 4.0 compliant.
    Block Diagram -- DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
  • LPDDR4X / LPDDR4 Controller
    • Maximizes bus efficiency via Look- Ahead command processing, Bank Management and Auto-Precharge
    • Minimal latency achieved via parameterized pipelining
  • SDRAM LPDDR5/4x/4/3/2 Host Controller & PHY - TSMC 16nm 16FFC,FF
    • DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • Built-in Gate Training, Read/Write Leveling, and VREF Training
    • Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • SDRAM DDRx & LPDDR4x Host Controller & PHY - TSMC 12nm 12FFC,FFC+
    • + DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • + Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • + Built-in Gate Training, Read/Write Leveling, and VREF Training
    • + Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • DDRx & LPDDRx DRAM Combo Memory Controller
    • + DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • + Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • + Built-in Gate Training, Read/Write Leveling, and VREF Training
    • + Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • LPDDR4 Controller IP
    • Supports LPDDR4 protocol standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C, JESD209-4X and JESD209-4Y (Proposed) Specification.
    • Compliant with DFI version 4.0 or 5.0 Specification.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
  • LPDDR3/4 Memory Controller IP
    • a. DDR3-LPDDR3 and DDR4-LPDDR4 modes up to 2133Mbps, and 2800Mbps,respectively
    • b. x16/x32 data path interface extendable
    • c. JEDEC 1.2V SSTL I/Os and 1.1V LVSTL I/Os
    • d. Multiple drive strengths adjustable
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