LPDDR4 Controller IP

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Compare 15 LPDDR4 Controller IP from 7 vendors (1 - 10)

LPDDR4/3, DDR4/3 Memory Controller IP
- Compliant with JEDEC standards for LPDDR4/3, DDR4/3
- DRAM rank of up to 4
- Lock-step-based controlling of multiple DRAM devices up to x64 DQ width
- Support for dynamic DRAM frequency scaling
Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
LPDDR Controller supporting LPDDR5X, LPDDR5, and LPDDR4X
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Multiport Arm® AMBA® interface (AXI™4 / AXI™ 3) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys LPDDR5X/5/4X PHY and other LPDDR5X/5/4X PHYs
- Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
LPDDR Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Multiport Arm® AMBA® interface (AXI™4 / AXI™ 3) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys LPDDR5X/5/4X PHY and other LPDDR5X/5/4X PHYs
- Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
LPDDR Controller ASIL B Compliant supporting LPDDR5X, LPDDR5 and LPDDR4X for Automotive Applications
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Multiport Arm® AMBA® interface (AXI™4 / AXI™ 3) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys LPDDR5X/5/4X PHY and other LPDDR5X/5/4X PHYs
- Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
LPDDR Secure Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Multiport Arm® AMBA® interface (AXI™4 / AXI™ 3) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys LPDDR5X/5/4X PHY and other LPDDR5X/5/4X PHYs
- Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
- Support DDR3 / DDR3L / DDR4/ 3DS DDR4/ LPDDR4 / MRAM
- Support x8/x16/x32 DRAM data bus configuration (programmable)
- Support Multi-Ranks DRAM configuration
- DDR base on DFI spec 4.0 compliant.
LPDDR4X / LPDDR4 Controller
- Maximizes bus efficiency via Look- Ahead command processing, Bank Management and Auto-Precharge
- Minimal latency achieved via parameterized pipelining