Die to Die IP for Samsung
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Die to Die IP
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13
Die to Die IP
for Samsung
from 6 vendors
(1
-
10)
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UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Emerging Standard Knowledge
- Flexibly Configurable
- Best in Class PPA
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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- Efficiency
- Composability
- Programmability
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UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
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Die-2-die interfaces for chiplets
- Analog I/Os
- ESD Power protection
- Ground pads
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40G Ultralink D2D PHY for Samsung 7LPP
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- BIST features ensure Known Good Die (KGD)
- Sideband for link management
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INNOLINK-C Controller
- General Features
- DFI Features
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INNOLINK-C PHY
- LPDDR5 like interface with IO voltage 0.4V and core power supply 0.9V
- 12Gbps for maximum IO speed in HLMC 28nm process
- Default 64-bit DQ Tx+ 64-bit DQ Rx per module, module number can be 1/2/4/8/16 or more
- Burst data, forward clock, no CDR
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INNOLINK-B Controller
- General Features
- DFI Features
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INNOLINK Chiplet PHY&Controller
- Innolink-A
- Meets the performance, efficiency and reliability requirements of B2B/C2C interconnects
- Already silicon proven
- Delivers 56Gbps/pair with -36dB insertion loss
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INNOLINK-B PHY
- Support both Die2Die and Chip2Chip application
- GDDR6 like interface with IO voltage is core power supply (0.8V for TSMC 12nm)
- 24Gbps for maximum IO speed
- Default 16bit DQ Tx+ 16bit DQ Rx per module, module number can be 1/2/4/8/16 or more