Die to Die IP for Samsung
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Die to Die IP
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16
Die to Die IP
for Samsung
from 6 vendors
(1
-
10)
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UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Emerging Standard Knowledge
- Flexibly Configurable
- Best in Class PPA
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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- Efficiency
- Composability
- Programmability
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UCIe-S PHY for Standard Package (x16) in SS SF4X, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
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UCIe-A PHY for Advanced Package (x64) in SS SF4X, North/South Orientation with 8collumn module configuration
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
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UCIe-A (Gen2) PHY for Advanced Package (x64) in SS SF4X, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
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UCIe-S PHY for Standard Package (x16) in SS SF5A, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
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UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
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Die-2-die interfaces for chiplets
- Analog I/Os
- ESD Power protection
- Ground pads
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40G Ultralink D2D PHY for Samsung 7LPP
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- BIST features ensure Known Good Die (KGD)
- Sideband for link management
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INNOLINK-C Controller
- General Features
- DFI Features