A/D Converter (ADC) IP for Samsung

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Compare 7 A/D Converter (ADC) IP for Samsung from 4 vendors (1 - 7)
  • Digital Cell Library Samsung
    • Compact standard cell library targeting a wide range of foundries and processes
    • Customised for low-power, ultra-low-leakage, high density or high-speed applications with choices of:
    • Power Management library for low-power designs
    • Timing models for customisable range of PVT
    Block Diagram -- Digital Cell Library Samsung
  • 8-10 bit SAR ADC Samsung
    • Resolution: 8b, 10b
    • Sampling Rate (Fs): 1 Msps to 20Msps
    • Input Signal Bandwidth: Fs/2
    • SINAD1: Typ 54dB
    Block Diagram -- 8-10 bit SAR ADC Samsung
  • 12-bit SAR ADC Samsung
    • Resolution: 12 bits
    • Sampling Rate (Fs) 1: Up to 64 MSPS
    • Input Signal Bandwidth: Fs/2
    • SINAD1: Typ 69 dB
    Block Diagram -- 12-bit SAR ADC Samsung
  • SAR ADC
    • Area: 0.135mm2 with IO and ESD
    • Note: The area parameter is for reference only. Please refer to the final LEF file for the actual values.
    • 10-bit resolution
    • Up to 1MS/s sampling rate
  • Video DAC (10bits, 300Msps)
    • Area: 0.232mm2 (400um x 580um) including IO and ESD
    • 10-bit 1-channel current-steering DAC
    • Up to 300MHz update rate
    • Support single-ended or differential output
  • 12bit 1MSPS SAR ADC
    • SAMSUNG 65nm CMOS
    • Wide Operating Range
  • 12-Bit High-Performance DAC for 802.11ac
    • Integrated voltage reference
    • Standard CMOS implementation
    • Yield enhanced
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