USB PD IP

Overview

Key Features

• Compliant with USB Power Delivery Specification 3.1/3.0/2.0 and 1.0
• Supports Cable plug communication
• Supports all Resets: Hard, Soft and Cable Resets
• Supports all types of packets.
• Supports BFSK and BMC signaling of physical layer
• Support BIST.
• Supports Timers as per specification
• Supports Counters as per specification
• Supports data role swap and power role swap
• Supports Structured and Unstructured VDM
• Supports Device and System Policy
• Supports injecting timing variations in physical layer.
• Supports all Swappings: Power role, Data role, Fast power role and Vconn swap
• Supports chunked transaction
• Supports included extended power supply capabilities and status.
• Fully synthesizable.
• Static synchronous design.
• Positive edge clocking and no internal tri-states.
• Scan test ready.
• Simple interface allows easy connection to microprocessor/microcontroller devices.

Benefits

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The USB PD interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User s Guide and Release notes.

Technical Specifications