Synthesized RTL of SRAM/NOR memory controller with ECC IP-core (AXI interface)

Key Features

• • Configurable timing parameters exchange with SRAM- NOR-memory;
• • Configurable to support up to 6 banks of memory;
• • Configurable to support up to 26 bit address;
• • 32-bit data bus;
• • System interface - AXI 3.0 or MCIF II;
• • APB 3.0 interface for configuration;
• • Support ECC (error-correcting code - corrects a single error and detects double errors on a 32-bit data).

Benefits

• • The choice of interface for connecting to various systems (interface - AXI 3.0 or MCIF II);
• • Easy to integrate with standard AXI 3.0 or MCIF II interface and simple APB 3.0 interface for programming;
• • Wide possibilities of controller configuration;
• • The maximum data reading speed 4 byte per 1 cycle, maximum write speed 4 bytes per 2 cycles.

Applications

• • Mobile devices;
• • Portable devices;
• • Many categories of industrial and scientific subsystems, automotive electronics, and similar.

Technical Specifications