On-chip Nonvolatile AHB Memory Controller
Overview
CoreAhbNvm provides an AHB bus interface and CFI software interface to the embedded nonvolatile memory blocks within Microsemi's Fusion devices, enabling software running on an AHB-based microprocessor to read, write, and erase embedded Flash memory. CoreAhbNvm implements a standard Slave AHB Bus 32-bit hardware interface. This IP core is designed to provide a functional subset of the Common Flash Interface (software interface only) with emphasis given to minimize design size.
Key Features
- Provides an Industry-Standard Software Interface to Microsemi Fusion Flash Memory
- Implements a Subset of the Common Flash Memory Interface Specification Release 2.0
- Implements Standard Slave AHB Bus Hardware Interface
- Supports Read, Automatic Write and Erase, and Status Operations
- 32-Bit Interface, Allowing Byte, Half-Word, or Word Accesses to NVM
- Ability to Logically Merge Multiple Fusion NVM Blocks into One Large Area of NVM
- Supplied in Libero Gold IP Core Bundle
Technical Specifications
Related IPs
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- DDR1 DDR2 SDRAM Memory Controller
- On-chip AHB SRAM Memory Controller
- On-chip Nonvolatile APB Memory Controller
- Multi-Port Memory Controller (DDR/DDR2/SDRAM)
- Avalon Multi-port DDR2 Memory Controller