On-chip Nonvolatile APB Memory Controller
Overview
CoreApbNvm allows advanced microcontroller bus architecture (AMBA) Peripheral Bus (APB) access to the Microsemi Fusion nonvolatile memory (NVM), using a simple register-based access scheme. The core is designed to be configurable for use in various applications, using variable APB bus widths and a number of NVM instances (where supported). In addition, CoreApbNvm contains an Init/Config block which is used on reset to initialize RAM with the contents of NVM0. After reset, the Init/Config block can also be used to copy a user-specified number of words from NVM, starting at a user-specified base address.
Key Features
- Fully AMBA 2 APB-compliant
- Compatible with AMBA 3 APB
- Multiple memory sizes and variable number of NVM blocks
- Configurable 8-, 16-, or 32-bit data bus size
- Configurable APB address width in range of 8 to 32 bits
- Init/Config block for fetching data from NVM to RAM, primarily for CoreABC soft-mode initialization
- Remapping function via Init/Config block to load RAM from different addresses of NVM
- Register controlled auto increment mode
Technical Specifications
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