On-chip AHB SRAM Memory Controller
Overview
CoreAhbSram provides an AHB bus interface to the embedded SRAM memory blocks within Microsemi's Flash devices. In these devices, software running on an AHB-based microprocessor will be able to read and write the embedded SRAM. CoreAhbSram implements a standard Slave AHB Bus 32-bit hardware interface. The core supports the ability to logically merge multiple SRAM blocks into one large area of SRAM.
Key Features
- Optimized for use with Microsemi Flash FPGAs
- Implements Standard Slave AHB Bus Hardware Interface
- 32-Bit Interface, Allowing Byte, Halfword, or Word Accesses to SRAM
- Interfaces to Synchronous or Asynchronous SRAM
- Ability to Logically Merge Multiple SRAM Blocks into One Large Area of SRAM
- Supplied in SysBASIC Core Bundle
Technical Specifications
Related IPs
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- DDR1 DDR2 SDRAM Memory Controller
- On-chip Nonvolatile AHB Memory Controller
- AHB Internal SRAM Controller
- Multi-Port Memory Controller (DDR/DDR2/SDRAM)