MIPI M-PHY Gear 5 for TSMC N3E

Overview

The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v4.1 specification, supports multiple gears and a broad range of high-speed interfaces for applications including the JEDEC Universal Flash Storage (UFS), and the MIPI Low Latency Interface (LLI) and UniPro interfaces. By providing an application-oriented M-PHY IP that operates at multiple speeds and is interoperable with multiple protocols, Synopsys enables designers to “future-proof” their designs, while reducing the risk and cost of integrating MIPI interfaces into baseband, application processors and mobile integrated circuits (ICs).
When the Synopsys MIPI M-PHY IP is combined with the Synopsys Universal Flash Storage (UFS) Host Controller IP and Synopsys MIPI UniPro Controller IP, Synopsys provides a single vendor UFS IP solution that designers can easily integrate into application processors with less risk, while speeding time-to-market of advanced SoCs and device integrated circuits (ICs).

Key Features

Extended Reference clock support: 19.2, 26, 38.4 and 52MHz
Common lane configuration support for mobile IC applications
Fast entering and recovery from/to low-power modes
Optimized EMI performance through the use of slew rate control and dithering
Large and small amplitude
Sophisticated clock recovery mechanism
Power efficient clock circuitry for high-speed and low-speed clock generation
Advanced test features simplifies debug and production test procedures

Benefits

Compliant with MIPI M-PHY v4.1 specification
Supports MIPI LLI, UniPro, JEDEC UFS protocols
Supports High-Speed (HS) Gear1, Gear2, Gear3 A/B, and Gear 4 A/B modes
Supports M-PHY Type-I
Modular architecture allows multiple lane configuration • Low-speed Pulse-width Modulation (PWM) Gear1 to Gear5 in Type-I LS implementation
Low-power operation, small area and low latency
Future-proof for upcoming protocol enhancements
Supports advanced process technologies
Easily integrates with DesignWare MIPI UniPro and UFS Host

Applications

Chip-to-chip low-power interconnects
Smartphones
Tablets, ultrabooks, netbooks
Gaming
Digital cameras, camcorders
Storage
Wireless communication
Set-top boxes
Smart TVs
Automotive ADAS and infotainment
Drones
Augmented/virtual reality

Deliverables

Databook
Application notes
Integration guidelines
Verilog behavioral model
Abstract LEF and timing LIB files
GDSII layout database

Technical Specifications

Foundry, Node

TSMC N3E

Availability

Contact the Vendor

TSMC

Pre-Silicon: 3nm

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