MIPI C-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP

Overview

The MXL-CPHY-CSI-2-TX+ is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master supporting camera interface CSI-2. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.

Key Features

Supports MIPI Specification for C-PHY Version 1.1
80 Msps to 2.5 Gsps data rate in high speed mode
Consists of One Lane
10 Mbps data rate in low-power mode
Low power dissipation
Testability support

Benefits

Comprehensive embedded DFT features for allowing cost-effective high-volume manufacturing tests
Supports full-speed internal loopback testability with minimal area overhead for high-volume manufacturing tests

Block Diagram

Applications

Mobile
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC, 40ULP

Maturity

Available Upon Request

Availability

Now

TSMC

Pre-Silicon: 55nm G

Request Info