With sophisticated architecture and advanced technology, JESD204B X4 PMA IP is designed for low power and high performance application. It is fully compatible with JESD204B specification, and supports link rate from 1.6875Gbps to 16Gbps.
The IP is a JESD204B TX, it has four lanes and a common block. The maximum working data rate is 16Gbps for every lane.
JESD204B TX IP
Overview
Key Features
- X4 Lane Mode, support 1.6875G to 16Gbps (per lane)
- Serialization interface width
- PMA- MAC interface support 20/40 bit
- Shared common PLL based architecture
- Power Consumption
- ~180mW @typical (X4 PMA, typical corner, 25C, 0.975V/1.8V)
- Digitally-control-impedance termination resistors and On-chip resistance calibration
- Configurable TX output differential voltage swing
- Built-in TX De-Emphasis with post-cursor
- PLL Frequency Lock detection
- Support BIST, and Analog DC Testing
Benefits
- X4 Lane Mode, support 1.6875G to 16Gbps per lane
- Shared common PLL based architecture
- Configurable TX output differential voltage swing
- Support BIST, and Analog DC Testing
Applications
- ADC and DAC
- DSP
- FPGA
Deliverables
- GDSII&CDL Netlist
- Verilog Model
- LEF Layout Abstract(.LEF)
- Liberty Timing Models(.lib)
- Verify Results
- Specification
- Datasheet
- Integration Guideline
- Evaluation Plan
- Leading support for package design, SI&PI modeling and production test development
Technical Specifications
Foundry, Node
28nm
Maturity
Mass Production
Related IPs
- JESD204B
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- DDR3 Controller IP
- High-performance 2D (sprite graphics) GPU IP combining high pixel processing capacity and minimum gate count.
- FlexNoC 5 Interconnect IP
- BCH Encoder/Decoder IP Core