ColdFire V4 SPPC2 Processor Platform

Overview

Key Features

• On-board peripherals and their features include:
• FlexBus Controller
• Connects up to 6 on-chip or off-chip memories/devices
• Independently programmable transfer characteristics for each
• device (wait states, address setup/hold)
• Enhanced DMA (eDMA) Controller
• 16 independently programmable DMA channels
• Programmable channel arbitration modes
• Support for channel linking and scatter/gather operation
• Two Fast Ethernet Controllers, each of which provides
• 10/100 Mbps Ethernet support
• Half and full-duplex modes
• Media Independent Interface (MII) or 7-wire interface to
• Ethernet PHY
• Interrupt Controller
• 64 programmable interrupt sources, 7 of which are available
• for external interrupts
• Unique vector for each interrupt source
• Support for low-power mode wake-up
• Queued SPI (QSPI) module
• Programmable queue for up to 16 SPI transfers
• Four chip-select lines for up to 16 devices
• Programmable baud rate, before-and-after transfer delays,
• clock phase and polarity
• I2C interface module
• Support for the original Philips I2C bus protocol
• Support for baud rates up to 3.4 Mbps
• 3 UARTS
• Programmable clock source, data formats, and modes
• (normal/loopback)
• Error detection
• Four maskable interrupt conditions
• 4 DMA Timer modules
• Programmable clock source
• Programmable prescaler
• Programmable interrupt or DMA request upon timer event
• Miscellaneous Control Module (MCM)
• Software watchdog timer
• Reset status, low-power mode control, and core fault status
• registers

Benefits

• The ColdFire V4 SPPC2 Processor Platformfeatures software-controlled shutdown of selected clocks to support a variety of chip-level low-power modes:
• • Independent shutdown of selected peripheral clocks
• • Shutdown of the ColdFire V4 Core CPU clock in response to a
• ColdFire STOP instruction; the ColdFire V4 Core local SRAM
• Controller clock may optionally be kept running in STOP mode to
• support access to local SRAM from external AHB masters

Block Diagram

Video

Deliverables

• Verilog source code
• Integration testbench and tests
• Documentation
• Scripts for simulation and synthesis with commonly-used EDA
• tools

Technical Specifications