AXI bus fabric (AXI Master and Slaves)
Overview
CoreAXI supports up to four AXI master interfaces and 16 AXI slave interfaces. The number of AXI master and slaves to be connected is programmable through parameter configuration.The AXI protocol defines five independent channels: Write address channel, Read address channel, Write data channel, Write response channel, and Read data channel.
Key Features
- Multi-master AXI interconnect with support up to four AXI masters
- Up to 16 AXI slaves can be enabled or disabled through configuration. The slaves that are not enabled will be optimized during synthesis
- Supports additional 17th slave when huge slave or combined region is in use
- Provides 256 bytes to 256 MB of address space for each slave (Huge slave occupies 2 GB address space)
- Supports allocation of slave slots to a combined region slave interface
- AXI interface address width of 32-bits and data bus width of 64-/128-/256-bits
- Supports increment and wrap type bursts
- Round-robin arbitration scheme
- FEED_THROUGH mode for single slave and single master configuration
- Configurable register pipelining at the input and/or output stage
- Provides only four valid ID values in multi-master scenario
- Supports out-of-order completion for read transaction
- Supports maximum of 4 multiple outstanding write or read transactions
- Support maximum of four multiple outstanding read transactions to the same slave